The present invention relates to a semiconductor integrated circuit and an operation method of the same and, more particularly, relates to a technique useful to accurately set a frequency characteristic of a built-in filter.
In wireless mobile communication of a cellular phone or the like, it is expected that growth of sound service will slow down in future but, on the other hand, the mobile communication market will shift in future to multimedia service simultaneously providing images, sound, and data to support advanced bidirectional applications. Accordingly, a broadband mobile data network having a high average throughput enabling a wireless packet data access of a peak rate exceeding 384 kbps is being required.
Therefore, the wireless mobile communication shifts to the third generation which is more effective than the 2.5 generation between the second and third generation. The user peak data rate in the third generation is increased to 384 kbps in EDGE (Enhanced Data Rate for GSM Evolution) and 2 Mbps in cdma2000 and WCDMA. In downlink coupling of HSDPA (High Speed Downlink Packet Access) introduced in the WCDMA of the third generation, the high modulation level of 16 QAM is used and user peak data rate of 14.4 Mbps is theoretically possible. QAM stands for Quadrature Amplitude Modulation.
As the third-generation wireless network spreads, it is becoming more important to reduce cost and power consumption of a third-generation mobile cell terminal. The direct conversion receiver architecture is a popular system solution in an integrated platform of a third-generation mobile cell terminal properly using silicon process, circuit design technique, and architecture implementation.
A direct conversion receiver needs a channel selection filter configured by a low-pass filter in order to suppress a disturbing signal out of a channel. Non-patent document 1 describes that a direct conversion receiver does not need an image removing filter, and the channel selection filter is a low-pass filter which can be formed on a chip so that it is preferable to make a wireless transceiver at a high integration level. In the direct conversion receiver, a WCDMA reception signal is amplified by a low-noise amplifier. After that, the amplified signal is supplied to an I-signal mixer and a Q-signal mixer configuring a quadrature downconversion mixer, and an I local signal and a Q local signal having a phase difference of 90 degrees are supplied to the I-signal mixer and the Q-signal mixer. An I baseband signal generated from the I-signal mixer is supplied to a first channel selection filter and a first amplifier, and a Q baseband signal generated from the Q-signal mixer is supplied to a second channel selection filter and a second amplifier.
In the non-patent document 1, it is described that in a direct conversion WCDMA receiver, a baseband signal from an RF front end has to be filtered by a low-pass filter having a bandwidth of 2 MHz. To obtain an accurate filter characteristic such as a smallest bandpass ripple, an accurate value of apart is necessary. Since a frequency parameter of an active filter is set by an RC product, accurate values of the resistance and capacitance have to be realized. Therefore, a filter has to be electronically tunable, and an automatic tuning system is designed on a chip as a total filter system. That is, an RC active filter designed as the baseband channel selection filter of a direct conversion WCDMA receiver is controlled by an on-chip tuning circuit, and a parameter deviation is compensated so that the cutoff frequency is maintained at a design value.
The filter time constant is changed by using a binary weight 5-bit capacitance matrix, and a switch is realized by an NMOS transistor operating in a linear region. The frequency response is tuned by device layout of a resistor or a capacitor in a programmable array. The value of the array is designed by a digital code generated by an on-chip calibration circuit.
The frequency of each of integrators of a fifth-order Chebyshev low-pass filter is tuned by tuning the time constant of the integrator. A parallel-capacitance array topology including a single fixed element and N pieces of binary weight switching elements is employed.
Patent document 1 discloses a filter adjustment circuit for adjusting performance index (Q factor: Quality factor) of an active filter. An active filter includes an amplifier, an input resistor, a feedback resistor, and a feedback capacitor. The adjustment circuit includes a reference frequency generation circuit, a phase comparator, a reference voltage generation circuit, an amplitude comparator, and a control circuit. The reference frequency generation circuit generates a first signal having a filter cutoff frequency and a second signal having a phase different from that of the first signal, supplies the first signal to one of input terminals of the phase comparator, and supplies the second signal to the input terminal of the active filter. Since a third signal as a filter output signal of the active filter is supplied to the other input terminal of the phase comparator, the phase comparator compares the phase of the first signal and the phase of the third signal and determines whether the frequencies are the same or not. The third signal as a filter output signal of the active filter is supplied to one of input terminals of the amplitude comparator, and the reference voltage indicative of a predetermined amplitude value for specifying the Q factor generated from the reference voltage generation circuit is supplied to the other input terminal of the amplitude comparator. Consequently, the amplitude comparator compares the amplitude value of the third signal and the reference voltage and outputs the comparison result. The phase comparison result of the phase comparator and the amplitude comparison result of the amplitude comparator are supplied to the control circuit. The control circuit controls the feedback capacitor in the active filter, thereby adjusting the cutoff frequency of the active filter and, simultaneously, controls the feedback resistance of the active filter, thereby adjusting the Q factor of the active filter.
In the non-patent document 2 whose lead author is the single investor of the patent document 1, a filter tuning system similar to the filter adjustment circuit described in the patent document 1 is described. A fifth-order low-pass filter described in the non-patent document 2 is used as a low-pass filter having a bandwidth of 40 MHz of the direct conversion architecture for high-throughput enlargement-option for IEEE802.11n as one of wireless LAN standards devised by IEEE.
A filter tuning system illustrated in FIG. 14 of the non-patent document 2 includes a replica filter, a main filter, a reference signal/reference voltage generator, a phase comparator, an amplitude comparator, and a control circuit. The main filter is configured by a fifth-order Chebyshev active RC low-pass filter, and the replica filter is configured by a second-order low-pass filter as a replica of the main filter.
A replica input signal and a reference signal generated from the reference signal/reference voltage generator and having a phase difference of 90 degrees are supplied to the input terminal of the replica filter and one of input terminals of the phase comparator. A filter output signal from the replica filter is supplied to the other input terminal of the phase comparator and one of input terminals of the amplitude comparator, and reference voltage generated from the reference signal/reference voltage generator is supplied to the other input terminal of the amplitude comparator. A phase comparison result of the phase comparator and an amplitude comparison result of the amplitude comparator are supplied to the control circuit. By an output of the control circuit, the cutoff frequency of the replica filter and the Q factor of the replica filter are adjusted. In the adjustment, first, the cutoff frequency of the replica filter is adjusted by the resistance value of a total feedback resistor of the second-order low-pass filter as the replica filter. The total feedback resistor is coupled between the inversion input terminal of an amplifier in the first stage of the second-order low-pass filter as the replica filter and the output terminal of the signal inverter having the gain −1 of the output terminal of an amplifier in the second stage. In the adjustment, next, the Q factor of the replica filter is adjusted by the resistance value of a local feedback resistor of the second-order low-pass filter as the replica filter. The local feedback resistor is coupled to a feedback capacitor in series between the inversion input terminal and the output terminal of each of the amplifiers in the first and second stages in the second-order low-pass filter as the replica filter. In the adjustment, the parameter set in the replica filter which is tuned at last is copied into the main filter.